This Analog Mixed-Signal IC Design Engineering position will provide key contributions to state of the art PLLs for use in high performance networking and communications products. Responsibilities of the position include product definition, design, layout, lab verification, and releases to production.

Candidates must have a MSEE or Ph.D. with at least 5+ years or more of IC design work experience and extensive experience with high performance PLL design. An excellent track record in CMOS and/or BiCMOS IC design is required. Strong experience in designing low phase noise integer PLLs, fractional-N synthesizers, LC-VCOs, and state machines is required. Related experience in digital PLLs, crystal oscillators, VCXOS, on-chip regulators, DACs and ADCs are plusses. An understanding of transistor modeling and circuit noise theory is required. Digital design skills would be gladly welcomed, but are not required. Strong communication skills and a strong work ethic with the ability to work well individually and within a team environment are required. For consideration, please send your resume to Paul Montoya at (see below) today!